1. Technical Field
The present invention generally relates to integrated circuit design tools and in particular to integrated circuit design tools that optimize area performance and signal integrity in integrated circuits under a linear delay model.
2. Description of the Related Art
Existing methods have sought to improve the placement of negative-slack cells and latches of a circuit in a physical synthesis flow. While several solutions to this problem have existed, there are several drawbacks to these existing solutions. One drawback of existing solutions is that existing solutions consider only the placement of a single, movable gate within an integrated circuit design. Another drawback of existing solutions is that only one optimal placement location is outputted per movable gate.